The present invention relates to an imaging device incorporating a boosting circuit for generating a boosted voltage.
Batteries are used as power supplies in imaging devices, such as digital cameras, that employ solid state imaging devices (CCD image sensors). A battery has a predetermined output voltage width. Thus, an imaging device is provided with a boosting circuit and a regulating circuit to drive the CCD image sensor.
FIG. 1 is a schematic block diagram of a prior art imaging device 50. The imaging device 50 includes a CCD image sensor 1, a boosting circuit 2, a regulating circuit 3, a vertical driver circuit 4, a horizontal driver circuit 5, and a timing control circuit 6. In the imaging device 50, the boosting circuit 2 is located at the input side of the vertical driver circuit 4. The boosting circuit 2 boosts a power supply voltage, which is supplied from a battery, to a predetermined voltage to generate a boosted voltage. The boosted voltage drives the CCD image sensor 1.
The CCD image sensor 1 has a light receiving section (plane), which includes a matrix of a plurality of light receiving pixels. Each light receiving pixel receives light at the light receiving plane and performs photoelectric conversion to generate information charges. The CCD image sensor 1 stores the information charges in the light receiving pixels and then sequentially transfers the information charges in accordance with clock signals from the vertical driver circuit 4 and the horizontal driver circuit 5. An output section 1d, which is located at the final stage of the transfer route, converts the information charges to a voltage having a certain value to generate an image signal Y(t). There are different types of CCD imaging devices that transfer the information charges in different ways. For example, the CCD image sensor 1 is a frame transfer type CCD image sensor, which includes an imaging section 1i, a storage section 1s, a horizontal transfer section 1h, and an output section 1d. 
The boosting circuit 2, which is, for example a charge pump circuit, receives and boosts the power supply voltage VD, to generate a positive boosted voltage VOH (e.g., 5V) and a negative boosted voltage (e.g., −5V). The regulating circuit 3 receives the power supply voltage VD, generates a predetermined adjusted voltage (e.g., 2.0V to 2.5V) VK, and supplies the adjusted voltage VK to the horizontal driver circuit 5.
The vertical driver circuit 4 receives the boosted voltage VOL from the boosting circuit 2 and generates a frame transfer clock signal Øf and a vertical transfer clock signal Øv. The frame transfer clock signal Øf is provided to the imaging section 1i, and the vertical transfer clock signal Øv is provided to the storage section 1s. The frame transfer clock signal Øf and the vertical transfer clock signal Øv are generated in synchronism with a vertical synchronization signal VD and a horizontal synchronization signal HD, which are generated by the timing control circuit 6. This results in the information charges, which are stored in the imaging section 1i, simultaneously entering the storage section 1s. Further, the information charges in the storage section 1s are sequentially transferred to the horizontal transfer section 1h in units of single lines in synchronism with the horizontal synchronization signal HD.
The horizontal driver circuit 5 receives an adjusted voltage VK from the regulating circuit 3 and generates a horizontal transfer clock signal Øh and a reset clock signal Ør in accordance with the adjusted voltage VK. The horizontal transfer clock signal Øh is provided to the horizontal transfer section 1h, and the reset clock signal Ør is provided to the output section 1d. The horizontal transfer clock signal Øh and the reset clock signal Ør, which are generated in the horizontal driver circuit 5, are generated in synchronism with the horizontal synchronization signal HD. This results in a single line of information charges stored in the horizontal transfer section 1h being transferred to the output section 1d in units of single pixels during a single cycle (1H) of the horizontal synchronization signal HD.
The timing control circuit 6 includes a plurality of counters for counting a reference clock signal CK, which has a constant cycle. The timing control circuit 6 divides the reference clock signal CK by a predetermined ratio to generate the vertical and horizontal synchronization signals VD and HD. Further, the timing control circuit 6 receives a start trigger ST, which determines the timing for starting operation of the imaging device 50 (imaging mode). In, for example, an imaging device incorporated in electronic equipment, the start trigger signal ST is set because there is a standby mode. In the standby mode, the supply of power to the imaging device 50 is cut when a camera function of the electronic equipment is not in use. This reduces the power consumption of the electronic equipment.
The timing control circuit 6 generates a boosting clock signal CKV in response to the start trigger signal ST and provides the boosting clock signal CKV to the boosting circuit 2. Further, the timing control circuit 6 provides a boosting signal to the signal processing circuit (not shown), which performs a predetermined signal process on the output signal of the CCD image sensor 1. In other words, the timing control circuit 6 synchronizes the operation of each circuit in the imaging device 50 with the operation timing of the CCD image sensor 1.
FIG. 2 is a timing chart illustrating an operation of the boosting circuit 2 that prevents the boosting operation of the boosting circuit 2 from affecting the image signal Y(t). In FIG. 2, (H) represents a high level, and (L) represents a low level.
The start trigger signal ST is a signal for determining the timing for supplying power to the imaging device 50. For example, the supply of power to the imaging device 50 is enabled when the start trigger signal ST is high and stopped when the start trigger signal ST is low. Accordingly, at timing t0 in FIG. 2, the electronic equipment exits the standby mode and starts the imaging operation.
The image signal Y(t) is the output signal of the CCD image sensor 1. The image signal Y(t) is output when the horizontal synchronization signal HD is high. The output of the image signal Y(t) is stopped when the horizontal synchronization signal HD is low (blanking period). The image signal Y(t) corresponding to a single line is output during a single cycle of the horizontal synchronization signal HD. In FIG. 2, the image signal Y(t) corresponding to a single line is output in a single cycle of the horizontal synchronization signal HD at timings t1 to t2, t3 to t4, t5 to t6, and t7 to t9. The image signal Y(t) is output before the boosted voltage VOH reaches a predetermined voltage VH and invalidated by the signal processing circuit of the following stage during timings t1 to t2, t3 to t4, t5 to t6 and t7 to t9.
The boosting clock signal CKV, which is a clock signal for controlling the boosting operation of the boosting circuit 2, is generated during the blanking period of the horizontal synchronization signal HD, that is, during timings t1 to t2, t3 to t4, t5 to t6, and t7 to t9. Accordingly, the boosting circuit 2, which receives the boosting clock signal CKV, performs a boosting operation during the blanking period of the horizontal synchronization signal HD. The boosting operation is also performed during the blanking period of the horizontal synchronization signal HD for a negative output voltage VOL.
In, for example, Japanese Laid-Open Patent Publication No. 2001-218119, the applicant has disclosed the imaging device 50 that generates the boosting clock signal CKV during the blanking period of the horizontal synchronization signal HD or the vertical synchronization signal VD and prevents noise, which is produced by the boosting clock signal CKV, from mixing with the image signal Y(t).
However, the boosting operation of the boosting circuit 2 is performed intermittently in the imaging device 50. Thus, the boosted voltage VOH increases gradually. As a result, a certain amount of time is required for the voltage supplied to a drive circuit to reach the desired voltage value. This interferes with increasing the activating speed of the imaging device.